• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a method for manufacturing low voltage (NMOSLV, PMOSLV) and high voltage (NMOSHV, PMOSHV) MOS transistors of first and second types, comprising: providing a semiconductor layer (1); forming grid stacks (7, 9); forming first spacers (15A) into a first insulator; forming second spacers (17A) into a second insulator; removing the second spacers (17A) from the LV transistors (NMOSLV, PMOSLV); at the location of each transistor of the first type (NMOSLV, NMOSHV), etching the first insulator leaving all the spacers (15A, 17A) in place; growing a first semiconductor material (23) of the first type; depositing a layer (25) of the first insulation; at the location of each transistor of the second type (PMOSLV, PMOSHV), etching the first insulator leaving all the spacers (15A, 17A) in place; and growing a second semiconductor material (29) of the second type.
    公开号:FR3042907A1
    申请号:FR1560090
    申请日:2015-10-22
    公开日:2017-04-28
    发明作者:Sonarith Chhun；Emmanuel Josse；Gregory Bidal；Dominique Golanski；Francois Andrieu；Jerome Mazurier；Olivier Weber
    申请人:Commissariat a lEnergie Atomique CEA；STMicroelectronics Crolles 2 SAS；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    METHOD FOR MANUFACTURING MOS TRANSISTOR DEVICE
    Field
    The present application relates to a method of manufacturing a device comprising MOS transistors whose source and drain regions are thickened / epitaxially raised from a conductive layer.
    Presentation of the prior art
    In a device comprising MOS transistors formed from an SOI type semiconductor layer, ("semiconductor on insulator" - semiconductor on insulator when the semiconductor layer thickness (disposed on a buried layer of insulator) becomes low, commonly less than 20 nm, the source and drain regions of the transistors are generally thickened by epitaxial growth of a semiconductor material from the upper face of the semiconductor layer, and such epitaxially thickened source and drain regions can also be provided. in a device comprising MOS transistors formed from a semiconductor substrate, for example to constrain the channel forming region of the transistors and thereby improve their performance.
    In a device comprising epitaxially thickened source and drain region transistors, or epitaxial source and drain regions, the insulating spacers laterally lining the gate stack of each transistor then separate the epitaxially sourced and drained regions of the transistor. conductive grid areas. There is therefore a parasitic drain-source / gate capacitance whose value is essentially defined by the material or materials of the spacers and by the width of the spacers. There is also a risk of breakdown of the material of the spacers, the higher the transistor is intended to operate at high voltages.
    In the case where the device comprises transistors intended to operate at high voltages (HV transistors), the width of the spacers of the transistors of the device can be increased to reduce the risk of breakdown and the parasitic drain-source / gate capacitance of the transistors of the device. device. However, when the device also comprises transistors intended to operate at low voltages (LV transistors), this entails various disadvantages such as a degradation of the performance of the LV transistors.
    It would therefore be desirable to have a method for manufacturing a device comprising HV and LV MOS transistors with drain and source regions epitaxially, in which the spacers of the HV transistors are larger than those of the LV transistors of the same type. . summary
    Thus, an embodiment provides a method of manufacturing a device comprising low voltage, LV, and high voltage MOS transistors, HV, of a first and a second type, the method comprising the following successive steps: ) providing a semiconductor layer; b) forming gate stacks of MOSLV and HV transistors; c) forming first spacers by depositing a first layer of a first insulating material; d) forming second spacers in a second insulating material different from the first insulating material; e) removing the second spacers from the LV transistors (NMOSLV, PMOSLV); f) at the location of each transistor of the first type, etch the first layer to the semiconductor layer leaving all the spacers in place; g) growing a first doped semiconductor material of the first conductivity type from the exposed surface of the semiconductor layer; h) depositing a second layer of the first insulating material; i) at the location of each transistor of the second type, etching the first and second layers to the semiconductor layer leaving all the spacers in place; and j) growing a second doped semiconductor material of the second conductivity type from the exposed surface of the semiconductor layer.
    According to one embodiment, step d) comprises the deposition of a layer of the second material, and etching removal of the layer of the second material leaving in place the second spacers.
    According to one embodiment, the gate insulator of the gate stack of the LV transistors has an equivalent thickness less than the equivalent thickness of the gate insulator of the gate stack of the HV transistors.
    According to one embodiment, the semiconductor layer is based on an insulator and the thickness of the semiconductor layer is less than 20 nm.
    According to one embodiment, the first insulating material is silicon nitride and the second insulating material is silicon oxide.
    According to one embodiment, the transistors of the first type are N-channel and the transistors of the second type are P-channel.
    According to one embodiment, each of the first and second semiconductor materials is selected from the group consisting of silicon, germanium, silicon carbide and silicon-germanium.
    Another embodiment provides a device comprising low voltage, LV, and high voltage MOS transistors, HV, of a first and a second type, in which: the gate stack of each transistor rests on a semiconductor layer ; the source and drain regions of each transistor of the first type comprise a first doped semiconductor material of the first conductivity type bordering laterally on the gate stack of the transistor; the source and drain regions of each transistor of the second type comprise a second doped semiconductor material of the second conductivity type bordering laterally on the gate stack of the transistor; and each transistor comprises first spacers made of a first insulating material, the HV transistors further comprising second spacers made of a second insulating material different from the first material.
    According to one embodiment, the P type channel HV transistors comprise three successive elementary spacers: a first spacer made of a first insulating material, a second spacer made of a second insulating material different from the first insulating material, and a third spacer made from the first material. insulating.
    According to one embodiment, the first and third spacers meet on the side of the semiconductor layer to form a U.
    According to one embodiment, the gate insulator of the gate stack of the LV transistors has an equivalent thickness less than the equivalent thickness of the gate insulator of the gate stack of the HV transistors.
    According to one embodiment, the semiconductor layer rests on an insulator and the thickness of the semiconductor layer is less than 20 nm.
    According to one embodiment, the first insulating material is silicon nitride and the second insulating material is silicon oxide.
    According to one embodiment, the transistors of the first type are N-channel and the transistors of the second type are P-channel.
    According to one embodiment, each of the first and second semiconductor materials is selected from the group consisting of silicon, germanium, silicon carbide and silicon-germanium.
    Brief description of the drawings
    These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying FIGS. 1 to 8 which are sectional views schematically showing a structure to FIGS. successive steps of an embodiment of a manufacturing method.
    detailed description
    The same elements have been designated by the same references in the various figures and, in addition, the various figures are not drawn to scale. In the description which follows, the terms "superior", "lateral" and "vertex" refer to the orientation of the elements concerned in the corresponding figures. Unless otherwise indicated, the term "about" means to within 10%, preferably to within 5%.
    FIG. 1 is a sectional view schematically showing a SOI type structure at a stage of a method for manufacturing a device comprising four types of MOS transistors: high-voltage N-channel MOS transistors (NMOSHVj), transistors High voltage P channel MOS (PMOSHVj), low voltage P channel MOS transistors (PMOSLV), and low voltage N channel MOS transistors (NMOSLV).
    The structure comprises a semiconductor layer 1 resting on an insulating layer 3 disposed on a semiconductor substrate 5. A gate stack 7 has been formed at each NMOSHV and PMOSHV transistor location, and a gate stack 9 has been formed at each location of NMOSLV transistor and PMOSLV. The gate stacks 7 comprise a conductive zone 7A separated from the semiconductor layer 1 by a gate insulator 7B. The gate stacks 9 comprise a conductive zone 9A separated from the semiconductor layer 1 by a gate insulator 9B whose thickness (or the equivalent thickness) is less than that of the gate insulator 7B. In this example, each transistor location is delimited laterally by an insulating wall 11 passing through the semiconductor layer 1. As shown, a hard mask 13 may be disposed on the top of each gate stack 7 and 9, the mask hard 13 comprising for example a silicon oxide layer 13A coated with a silicon nitride layer 13B. By way of example, the material of the semiconductor layer 1 is chosen from the group comprising silicon, germanium, silicon-germanium, and silicon carbide, different semiconductor materials that can be used for the different types of semiconductors. transistors to be formed. The thickness of the semiconductor layer may be less than 20 nm, for example equal to 10 nm. The gate insulators 7B and 9B may be made of silicon oxide or an insulating material with a high dielectric constant ("high k"). In the step of FIG. 2, the structure has been coated with an insulating layer 15 and then with an insulating layer 17, the materials of the layers 15 and 17 being chosen to be selectively etchable with respect to each other . The material of the layer 15 notably borders each grid stack 7 and 9 and constitutes therein spacers 15A. The material of the layer 17 notably borders the spacers 15A and there constitutes spacers 17A. By way of example, the layer 15 is made of silicon nitride with a thickness that can be between 2.5 and 10 nm, for example 5 nm, and the layer 17 is made of silicon oxide with a thickness that can be included between 10 and 20 nm, for example 15 nm. In the step of FIG. 3, an anisotropic etching of the layer 17, for example a reactive ion etching, was carried out so as to leave the spacers 17A and the layer 15 in place. A resin layer 19 was then deposited. then etched to cover the structure at the location of each NMOSHV and PMOSHV transistor. In the step of FIG. 4, the spacers 17A bordering the gate stacks 9 of the NMOSLV and PMOSLV transistors have been eliminated. The resin 19 covering the NMOSHV and PMOSHV transistors was removed and a resin layer 21 was deposited and etched to cover the structure at the location of each PMOSLV and PMOSHV transistor. The insulating layer 15 was then removed by anisotropic etching to the semiconductor layer 1, for example by reactive ion etching, the resin 21 serving as an etching mask. At the location of each NMOSHV and NMOSLV transistor, the upper face of the semiconductor layer 1 is exposed and the spacers 15A and 17A are left in place. In the step of Figure 5, the resin 21 has been removed. A semiconductor material 23, for example silicon or silicon carbide, doped in situ of type N has been grown epitaxially from the exposed portions of the upper face of the semiconductor layer 1 at the locations of the NMOSLV and NMOSHV transistors. At these locations, the semiconductor material 23 then borders the grid stacks 7 and 9 provided with their spacers. An insulating layer 25 was then deposited over the entire exposed surface of the structure. The material of the layer 25 is the same as that of the layer 15, for example silicon nitride. The thickness of the layer 25 may be between 2 and 5 nm, for example 3 nm. In the step of FIG. 6, a resin layer 27 has been deposited and etched so as to cover the structure at the location of each NMOSHV and NMOSLV transistor. The insulating layers 15, 17 and 25 were removed by anisotropic etching to the semiconductor layer, for example by reactive ion etching, the resin 27 serving as an etching mask. Thus, at the location of each PMOSHV and PMOSLV transistor, the spacers 15A and 17A are left in place and the upper face of the semiconductor layer 1 is exposed. In addition, as shown, portions 25A of the laterally bordering layer of the grid stacks 7 and 9 of the PMOSHV and PMOSLV transistors are left in place. In the step of Figure 7, the resin 27 has been removed. A semiconductor material 29, for example silicon or silicon-germanium, doped in situ of the P type, was grown epitaxially from the exposed portions of the upper face of the semiconductor layer 1 at the locations of the PMOSHV and PMOSLV transistors. Thus, at these locations, the material 29 laterally borders a gate stack 7 or 9. In the step of FIG. 8, portions of the layer 25 have been removed by anisotropic etching, for example by reactive ion etching so as to leave in place the spacers 15A and 17A, and the portions 25A. The hard mask 13 was then removed by isotropic etching.
    There is thus obtained a device comprising four types of transistor, namely NMOSHV, NMOSLV, PMOSHV and PMOSLV, the NMOSHV and PMOSHV transistors for example being designed to operate at voltages greater than 1.8 V, and the NMOSLV and PMOSLV transistors being example intended to operate at voltages of less than or equal to about 1 V. Each drain and source region of the NMOSLV and NMOSHV transistors is thickened by an epitaxial layer 23, and, analogously, each drain and source region of the PMOSLV and PMOSHV transistors is thickened by an epitaxial layer 29. gate 7 or 9 of each transistor is separated from the material 23 or 29 by spacers 15A, the gate stack 7 of each NMOSHV and PMOSHV transistor being further separated from the material 23 or 29 by spacers 17A.
    Since the set of spacers 15A and 17A is wider than the spacers 15A, the risk of breakdown of the NMOSHV and PMOSHV transistors is reduced compared to the case where these transistors comprise only 15A spacers such as NMOSLV and PMOSLV transistors.
    Because the spacers 15A of the NMOSLV, NMOSHV, PMOSLV and PMOSHV transistors and the spacers 17A of the NMOSHV and PMOSHV transistors are formed before the epitaxial steps, the epitaxy of the semiconductor material 23 is performed simultaneously for all the NMOSLV and NMOSHV transistors. and the epitaxy of the semiconductor material 29 is performed simultaneously for all PMOSLV and PMOSHV transistors.
    During the epitaxial step described in relation with FIG. 5, at the location of each PMOSLV and PMOSHV transistor, the layer 15 covers the upper face of the semiconductor layer 1 so that the semiconductor material 23 can not not grow there. Thus, the layer 15 serves as a mask during this epitaxial step in addition to being used to make the spacers 15A.
    Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, those skilled in the art can adapt the materials indicated above. For example, the semiconductor material 23 may be the same, with a type of opposite conductivity, as the material 29, and vice versa. In addition, the conductivity types of the previously described layers, regions, and materials can all be reversed. The order and number of steps of the method described above can be modified by those skilled in the art. For example, steps of preparation, or cleaning, of the upper face of the semiconductor layer 1 may be provided before each step of epitaxy.
    In addition, although a method has been described in which the semiconductor layer 1 is of the SOI type, this semiconductor layer may also correspond to a semiconductor substrate.
    Although this has not been described, it will be understood that during the steps of anisotropic etching of the layer 17, the layer 15 and / or the layer 25, or during any steps of preparation of the upper face of the semiconductor layer, the material of the spacers 17A may be partially etched. Those skilled in the art will then choose to deposit the material of the layer 17 with a sufficient thickness to obtain spacers 17A having a desired width, notwithstanding the aforementioned partial engravings. For example, in the process described above, when a step of preparing the upper face of the semiconductor layer 1 with a solution comprising hydrofluoric acid is provided before each epitaxy, a deposited layer 17 of silicon oxide with a thickness 15 nm can make it possible to obtain spacers 17A with a width of 6 nm.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    A method of manufacturing a device comprising low voltage MOS transistors, LV, NMOSLV, PMOSLV and HV, NMOSHV, PMOSHV of a first and a second type, the method comprising the steps of successive steps: a) providing a semiconductor layer (1); b) forming gate stacks (7, 9) of LV and HV MOS transistors; c) forming first spacers (15A) by depositing a first layer (15) of a first insulating material; d) forcing second spacers (17A) into a second insulating material different from the first insulating material; e) removing the second spacers (17A) from the LV transistors; f) at the location of each transistor of the first type (NMOSLV, NMOSHV), etching the first layer (15) to the semiconductor layer (1) leaving all the spacers (15A, 17A) in place; g) growing a first doped semiconductor material (23) of the first conductivity type from the exposed surface of the semiconductor layer (1); h) depositing a second layer (25) of the first insulating material; i) at the location of each transistor of the second type (PMOSLV, PMOSHV), etching the first (15) and second (25) layers to the semiconductor layer (1) leaving all the spacers (15A, 17A) in place ); and j) growing a second doped semiconductor material (29) of the second conductivity type from the exposed surface of the semiconductor layer (1).
    [2" id="c-fr-0002]
    2. Method according to claim 1, wherein step d) comprises the deposition of a layer (17) of the second insulating material, and etching removal of the layer of the second insulating material leaving in place the second spacers ( 17A).
    [3" id="c-fr-0003]
    3. Method according to claim 1 or 2, wherein the gate insulator (9B) of the gate stack (9) of the LV transistors has an equivalent thickness less than the equivalent thickness of the gate insulator (7B ) of the gate stack (7) of the HV transistors.
    [4" id="c-fr-0004]
    4. Method according to any one of claims 1 to 3, wherein the semiconductor layer is based on an insulator and the thickness of the semiconductor layer (1) is less than 20 nm.
    [5" id="c-fr-0005]
    5. Method according to any one of claims 1 to 4, wherein the first insulating material is silicon nitride and the second insulating material is silicon oxide.
    [6" id="c-fr-0006]
    6. Method according to any one of claims 1 to 5, wherein the transistors of the first type (NMOSHV, NMOSLV) are N-channel and the transistors of the second type (PMOSHV, PMOSLV) are P-channel.
    [7" id="c-fr-0007]
    The method of any one of claims 1 to 6, wherein each of the first and second semiconductor materials (23, 29) is selected from the group consisting of silicon, germanium, silicon carbide and silicon germanium.
    [8" id="c-fr-0008]
    An apparatus comprising low voltage MOS transistors, LV, (NMOSLV, PMOSLV) and high voltage, HV, (NMOSHV, PMOSHV) of a first and a second type, wherein: a gate stack (7, 9 ) of each transistor rests on a semiconductor layer (1); source and drain regions of each transistor of the first type (NMOSLV, NMOSHV) comprise a first doped semiconductor material (23) of the first conductivity type laterally lining the gate stack of the transistor; the source and drain regions of each transistor of the second type (PMOSLV, PMOSHV) comprise a second doped semiconductor material of the second conductivity type laterally lining the gate stack of the transistor; and each transistor comprises first spacers (15A) made of a first insulating material, the HV transistors (PMOSHV, NMOSHV) further comprising second spacers (17A) made of a second insulating material different from the first insulating material.
    [9" id="c-fr-0009]
    9. Device according to claim 8, wherein the P type channel HV transistors (PMOSHV) comprise three successive elementary spacers: a first spacer (15A) of a first insulating material, a second spacer (17A) of a second insulating material. different from the first insulating material and a third spacer (25A) to the first insulating material.
    [10" id="c-fr-0010]
    10. Device according to claim 9, wherein the first and third spacers meet on the side of the semiconductor layer (1) to form a U.
    [11" id="c-fr-0011]
    11. Device according to any one of claims 8 to 10, wherein the gate insulator (9B) of the gate stack (9) of the LV transistors has an equivalent thickness less than the equivalent thickness of the insulator. gate (7B) of the gate stack (7) of the HV transistors.
    [12" id="c-fr-0012]
    12. Device according to any one of claims 8 to 11, wherein the semiconductor layer is based on an insulator and the thickness of the semiconductor layer (1) is less than 20 nm.
    [13" id="c-fr-0013]
    13. Device according to any one of claims 8 to 12, wherein the first insulating material is silicon nitride and the second insulating material is silicon oxide.
    [14" id="c-fr-0014]
    14. Device according to any one of claims 8 to 13, wherein the transistors of the first type (NMOSHV, NMOSLV) are N-channel and the transistors of the second type (PMOSHV, PMOSLV) are P-channel.
    [15" id="c-fr-0015]
    15. Device according to any one of claims 8 to 14, wherein each of the first and second semiconductor materials (23, 29) is selected from the group consisting of silicon, germanium, silicon carbide and silicon-germanium.
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    同族专利:
    公开号 | 公开日
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    引用文献:
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    法律状态:
    2016-09-21| PLFP| Fee payment|Year of fee payment: 2 |
    2017-04-28| PLSC| Publication of the preliminary search report|Effective date: 20170428 |
    2017-09-21| PLFP| Fee payment|Year of fee payment: 3 |
    2018-09-19| PLFP| Fee payment|Year of fee payment: 4 |
    2019-09-19| PLFP| Fee payment|Year of fee payment: 5 |
    2020-09-17| PLFP| Fee payment|Year of fee payment: 6 |
    2021-09-22| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1560090A|FR3042907B1|2015-10-22|2015-10-22|METHOD FOR MANUFACTURING A MOS TRANSISTOR DEVICE|FR1560090A| FR3042907B1|2015-10-22|2015-10-22|METHOD FOR MANUFACTURING A MOS TRANSISTOR DEVICE|
    US15/296,205| US9876032B2|2015-10-22|2016-10-18|Method of manufacturing a device with MOS transistors|
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